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1 features ? fast read access time ? 120 ns fast byte write ? 200 s or 1 ms self-timed byte write cycle ? internal address and data latches ? internal control timer ? automatic clear before write direct microprocessor control ? ready/busy open drain output ? data polling low power ? 30 ma active current ? 100 a cmos standby current high reliability ? endurance: 10 4 or 10 5 cycles ? data retention: 10 years 5v 10% supply cmos and ttl compatible inputs and outputs jedec approved byte-wide pinout commercial and industrial temperature ranges description the at28c64 is a low-power, high-performance 8,192 words by 8-bit nonvolatile elec- trically erasable and programmable read only memory with popular, easy-to-use fea- tures. the device is manufactured with atmel ? s reliable nonvolatile technology. 64k (8k x 8) parallel eeproms at28c64 at28c64x rev. 0001h ? 12/99 pin configurations pin name function a0 - a12 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs rdy/busy ready/busy output nc no connect dc don ? t connect tsop top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 oe a11 a9 a8 nc we vcc rdy/busy (or nc) a12 a7 a6 a5 a4 a3 a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 lcc, plcc to p v i e w note: plcc package pins 1 and 17 are don ? t connect. 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a6 a5 a4 a3 a2 a1 a0 nc i/o0 a8 a9 a11 nc oe a10 ce i/o7 i/o6 4 3 2 1 32 31 30 14 15 16 17 18 19 20 i/o1 i/o2 vss dc i/o3 i/o4 i/o5 a7 a12 rdy/busy (or nc) dc vcc we nc (continued) pdip, soic to p v i e w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 rdy/busy (or nc) a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vcc we nc a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3
at28c64(x) 2 the at28c64 is accessed like a static ram for the read or write cycles without the need for external components. dur- ing a byte write, the address and data are latched inter- nally, freeing the microprocessor address and data bus for other operations. following the initiation of a write cycle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. the device includes two methods for detecting the end of a write cycle, level detection of rdy/busy (unless pin 1 is n.c.) and data polling of i/o 7 . once the end of a write cycle has been detected, a new access for a read or write can begin. the cmos technology offers fast access times of 120 ns at low power dissipation. when the chip is deselected the standby current is less than 100 a. atmel?s at28c64 has additional features to ensure high quality and manufacturability. the device utilizes error cor- rection internally for extended endurance and for improved data retention characteristics. an extra 32 bytes of eeprom are available for device identification or tracking. block diagram absolute maximum ratings* temperature under bias ................................ -55 c to +125 c *notice: stresses beyond those listed under ? absolute maximum ratings ? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability storage temperature ..................................... -65 c to +150 c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v voltage on oe and a9 with respect to ground ...................................-0.6v to +13.5v
at28c64(x) 3 device operation read: the at28c64 is accessed like a static ram. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in a high impedance state whenever ce or oe is high. this dual line control gives designers increased flexibility in preventing bus contention. byte write: writing data into the at28c64 is similar to writing into a static ram. a low pulse on the we or ce input with oe high and ce or we low (respectively) ini- tiates a byte write. the address location is latched on the falling edge of we (or ce ); the new data is latched on the rising edge. internally, the device performs a self-clear before write. once a byte write has been started, it will automatically time itself to completion. once a program- ming operation has been initiated and for the duration of t wc , a read operation will effectively be a polling operation. fast byte write: the at28c64e offers a byte write time of 200 s maximum. this feature allows the entire device to be rewritten in 1.6 seconds. ready/busy : pin 1 is an open drain rdy/busy output that can be used to detect the end of a write cycle. rdy/busy is actively pulled low during the write cycle and is released at the completion of the write. the open drain connection allows for or-tying of several devices to the same rdy/busy line. the rdy/busy pin is not con- nected for the at28c64x. data polling: the at28c64 provides data polling to signal the completion of a write cycle. during a write cycle, an attempted read of the data being written results in the complement of that data for i/o 7 (the other outputs are indeterminate). when the write cycle is finished, true data appears on all outputs. write protection: inadvertent writes to the device are protected against in the following ways: (a) v cc sense ? if v cc is below 3.8v (typical) the write function is inhibited; (b) v cc power on delay ? once v cc has reached 3.8v the device will automatically time out 5 ms (typical) before allowing a byte write; and (c) write inhibit ? holding any one of oe low, ce high or we high inhibits byte write cycles. chip clear: the contents of the entire memory of the at28c64 may be set to the high state by the chip clear operation. by setting ce low and oe to 12 volts, the chip is cleared when a 10 msec low pulse is applied to we . device identification: an extra 32 bytes of eeprom memory are available to the user for device iden- tification. by raising a9 to 12 0.5v and using address locations 1fe0h to 1fffh the additional bytes may be written to or read from in the same manner as the regular memory array.
at28c64(x) 4 notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 3. v h = 12.0v 0.5v. dc and ac operating range at28c64-12 at28c64-15 at28c64-20 at28c64-25 operating temperature (case) com. 0 c - 70 c0 c - 70 c0 c - 70 c0 c - 70 c ind. -40 c - 85 c-40 c - 85 c-40 c - 85 c-40 c - 85 c v cc power supply 5v 10% 5v 10% 5v 10% 5v 10% operating modes mode ce oe we i/o read v il v il v ih d out write (2) v il v ih v il d in standby/write inhibit v ih x (1) x high z write inhibit x x v ih write inhibit x v il x output disable x v ih x high z chip erase v il v h (3) v il high z dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc + 1v 10 a i lo output leakage current v i/o = 0v to v cc 10 a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc + 1.0v 100 a i sb2 v cc standby current ttl ce = 2.0v to v cc + 1.0v com. 2 ma ind. 3 ma i cc v cc active current ac f = 5 mhz; i out = 0 ma ce = v il com. 30 ma ind. 45 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma = 4.0 ma for rdy/busy 0.45 v v oh output high voltage i oh = -400 a 2.4 v
at28c64(x) 5 ac read waveforms (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (c l = 5 pf). 4. this parameter is characterized and is not 100% tested. input test waveforms and measurement level output test load note: 1. this parameter is characterized and is not 100% tested. ac read characteristics symbol parameter at28c64-12 at28c64-15 at28c64-20 at28c64-25 units min max min max min max min max t acc address to output delay 120 150 200 250 ns t ce (1) ce to output delay 120 150 200 250 ns t oe (2) oe to output delay 10601070108010100ns t df (3)(4) ce or oe high to output float 045050055060ns t oh output hold from oe , ce or address, whichever occurred first 0000ns t r , t f < 20 ns pin capacitance f = 1 mhz, t = 25 c (1) symbol typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v
at28c64(x) 6 ac write waveforms we controlled ce controlled ac write characteristics symbol parameter min max units t as , t oes address, oe setup time 10 ns t ah address hold time 50 ns t wp write pulse width (we or ce ) 100 1000 ns t ds data setup time 50 ns t dh , t oeh data, oe hold time 10 ns t cs , t ch ce to we and we to ce setup and hold time 0 ns t db time to device busy 50 ns t wc write cycle time (option available) at 2 8 c 6 4 1 m s at28c64e 200 s
at28c64(x) 7 notes: 1. these parameters are characterized and not 100% tested. 2. see ? ac read characteristics ? . data polling waveforms chip erase waveforms t s = t h = 1 sec (min.) t w = 10 msec (min.) v h = 12.0 0.5v data polling characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns
at28c64(x) 8
at28c64(x) 9 at28c64 ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 120 30 0.1 at28c64-12jc at28c64-12pc at28c64-12sc at28c64-12tc 32j 28p6 28s 28t commercial (0 c to 70 c) 45 0.1 at28c64-12ji at28c64-12pi at28c64-12si at28c64-12ti 32j 28p6 28s 28t industrial (-40 c to 85 c) 150 30 0.1 at28c64-15jc at28c64-15pc at28c64-15sc at28c64-15tc 32j 28p6 28s 28t commercial (0 c to 70 c) 45 0.1 at28c64-15ji at28c64-15pi at28c64-15si at28c64-15ti 32j 28p6 28s 28t industrial (-40 c to 85 c) 200 30 0.1 at28c64-20jc at28c64-20pc at28c64-20sc at28c64-20tc 32j 28p6 28s 28t commercial (0 c to 70 c) 45 0.1 at28c64-20ji at28c64-20pi at28c64-20si at28c64-20ti 32j 28p6 28s 28t industrial (-40 c to 85 c) 250 30 0.1 at28c64-25jc at28c64-25pc at28c64-25sc at28c64-25tc 32j 28p6 28s 28t commercial (0 c to 70 c) 45 0.1 at28c64-25ji at28c64-25pi AT28C64-25SI at28c64-25ti 32j 28p6 28s 28t industrial (-40 c to 85 c) package type 32j 32-lead, plastic j-leaded chip carrier (plcc) 28p6 28-lead, 0.600" wide, plastic dull inline package (pdip) 28s 28-lead, 0.300" wide, plastic gull wing, small outline (soic) 28t 28-lead, plastic thin small outline package (tsop) options blank standard device: endurance = 10k write cycles; write time = 1 ms e high endurance option: endurance = 100k write cycles; write time = 200 s
at28c64(x) 10 at28c64x ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 150 30 0.1 at28c64x-15jc at28c64x-15pc at28c64x-15sc at28c64x-15tc 32j 28p6 28s 28t commercial (0 c to 70 c) 45 0.1 at28c64x-15ji at28c64x-15pi at28c64x-15si at28c64x-15ti 32j 28p6 28s 28t industrial (-40 c to 85 c) 200 30 0.1 at28c64x-20jc at28c64x-20pc at28c64x-20sc at28c64x-20tc 32j 28p6 28s 28t commercial (0 c to 70 c) 45 0.1 at28c64x-20ji at28c64x-20pi at28c64x-20si at28c64x-20ti 32j 28p6 28s 28t industrial (-40 c to 85 c) 250 30 0.1 at28c64x-25jc at28c64x-25pc at28c64x-25sc at28c64x-25tc 32j 28p6 28s 28t commercial (0 c to 70 c) 45 0.1 at28c64x-25ji at28c64x-25pi at28c64x-25si at28c64x-25ti 32j 28p6 28s 28t industrial (-40 c to 85 c) valid part numbers the following table lists standard atmel products that can be ordered. device numbers speed package and temperature combinations at28c64 x 12 jc, ji, pc, pi, sc, si, tc, ti at28c64 x 15 jc, ji, pc, pi, sc, si, tc, ti at28c64 x 20 jc, ji, pc, pi, sc, si, tc, ti at28c64 x 25 jc, ji, pc, pi, sc, si, tc, ti die products reference section: parallel eeprom die products package type 32j 32-lead, plastic j-leaded chip carrier (plcc) 28p6 28-lead, 0.600" wide, plastic dull inline package (pdip) 28s 28-lead, 0.300" wide, plastic gull wing, small outline (soic) 28t 28-lead, plastic thin small outline package (tsop)
at28c64(x) 11 packaging information .045(1.14) x 45? pin no. 1 identify .025(.635) x 30? - 45? .012(.305) .008(.203) .021(.533) .013(.330) .530(13.5) .490(12.4) .030(.762) .015(.381) .095(2.41) .060(1.52) .140(3.56) .120(3.05) .032(.813) .026(.660) .050(1.27) typ .553(14.0) .547(13.9) .595(15.1) .585(14.9) .300(7.62) ref .430(10.9) .390(9.90) at contact points .022(.559) x 45? max (3x) .453(11.5) .447(11.4) .495(12.6) .485(12.3) 1.47(37.3) 1.44(36.6) pin 1 .566(14.4) .530(13.5) .090(2.29) max .005(.127) min .065(1.65) .015(.381) .022(.559) .014(.356) .065(1.65) .041(1.04) 0 15 ref .630(16.0) .590(15.0) .690(17.5) .610(15.5) .012(.305) .008(.203) .110(2.79) .090(2.29) .161(4.09) .125(3.18) seating plane .220(5.59) max 1.300(33.02) ref *controlling dimension: millimeters index mark area 0.55 (0.022) bsc 0.20 (0.008) 0.10 (0.004) 7.15 (0.281) ref 8.10 (0.319) 7.90 (0.311) 1.25 (0.049) 1.05 (0.041) 0.27 (0.011) 0.18 (0.007) 11.9 (0.469) 11.7 (0.461) 13.7 (0.539) 13.1 (0.516) 0 5 0.20 (0.008) 0.15 (0.006) ref 0.70 (0.028) 0.30 (0.012) 32j , 32-lead, plastic j-leaded chip carrier (plcc) dimensions in inches and (millimeters) jedec standard ms-016 ae 28p6 , 28-lead, 0.600" wide, plastic dual inline package (pdip) dimensions in inches and (millimeters) jedec standard ms-011 ab 28s , 28-lead, 0.300" wide, plastic gull wing small outline (soic) dimensions in inches and (millimeters) 28t , 28-lead, plastic thin small outline package (tsop) dimensions in millimeters and (inches)*
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